uvm/ systemverilog design verification engineer Jobs - 82
AI Research Scientist, VLLM (vision large language models)
Meta - New York,NY
Employment Type : Full-Time
Summary: •Lead, collaborate, and execute on research that pushes forward the state of the art in multimodal reasoning and generation research.•Work towards long-term ambitious research goals, while identifying...
Senior Applied Scientist - Large Language Models / Generative AI
Datadog - New York,NY
Employment Type : Full-Time
Senior Data Scientist - Large Language Models / Generative AI Our Data Science Large Language Models team uses advanced generative AI technologies to create powerful features within the Datadog application. Our...
Hybrid Senior Electrical Engineer
ZipRecruiter - Scotchtown,NY
Employment Type : Full-Time
Job DescriptionJob Description Compensation: Estimated $115,000 to $160,000 annual salary based on experience with potential for increase upon obtaining PE license Hybrid Location: Midland Park, NJ, or...
Software Engineer, Systems New York, NY • Software Engineering • Design +1 more New York, NY So[...]
Meta - New York,NY
Employment Type : Full-Time
Meta Platforms, Inc. (Meta), formerly known as Facebook Inc., builds technologies that help people connect, find communities, and grow businesses. When Facebook launched in 2004, it changed the way people connect. Apps and services like Messenger,...
Lead Software Engineer
Harnham - New York,NY
Employment Type : Full-Time
This range is provided by Harnham. Your actual pay will be based on your skills and experience — talk with your recruiter to learn more. Base pay range $185,000.00/yr - $215,000.00/yr Direct message the job poster from...