About the company:
- Our client is a global leader in the development of network-on-chip solutions, and we are expanding our innovative team in Krakow, Poland.
- Krakow offers a vibrant, dynamic, and culturally rich environment, combined with excellent work-life balance and numerous opportunities for personal and professional growth.
Key Responsibilities:.
- We are seeking an experienced, results-oriented, and rigorous senior hardware verification engineer to join our HSI validation team with leading-edge Electronic Design Automation (EDA) expertise..
- You will work on the most advanced System-on-Chip (SoC) assembly and HSI flows with the aim to influence the development environment, the architecture, the verification, and everything in between..
- Developed and executed simulation-based verification tests for the Arteris Register Bank compiler tool, compatible with RTL simulators (Cadence, Synopsys, Siemens)..
- Created validation tests using Python for qualifying Register tool collaterals (IP-XACT, C headers, documentation).. Maintained and improved tests in the CI pipeline, enhancing automation and metrics..
- Contributed to refining processes, methodologies, and metrics..
- Used tools like Confluence and Jira for specifications, documentation, and project tracking.
Requirements:.
- 7+ years of industry experience as RTL verification engineer.
- Strong expertise in UVM framework.
- Understanding of hardware RTL design languages (VHDL, Verilog, SystemVerilog). Proficient with Python scripting language.
- Knowledge of IP-XACT standard, C-HAL, and equivalence checking tools is a plus..
- Good written and verbal communication skills in English Required experience: . Engineering degree in computer science or a related field.
Language(s) Requirements: . Fluent English . Proficiency in French would be a plus