System Verilog UVM Design Verification Test Engineer - US Tech Solutions : Job Details

System Verilog UVM Design Verification Test Engineer

US Tech Solutions

Job Location : New York,NY, USA

Posted on : 2025-06-21T13:11:42Z

Job Description :
Job Description:The project relates to the design and verification of a custom controller for analog components. The controller has interfaces such as SPI, Ethernet and AXI to drive the internal components and send data.Responsibilities:UVM...
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