System Verilog UVM Design Verification Test Engineer - US Tech Solutions : Job Details

System Verilog UVM Design Verification Test Engineer

US Tech Solutions

Job Location : Goleta,CA, USA

Posted on : 2025-05-11T00:53:34Z

Job Description :
System Verilog UVM Design Verification Test Engineer

The project involves the design and verification of a custom controller for analog components. The controller interfaces with SPI, Ethernet, and AXI to drive internal components and transmit data.

Job Description:

The project involves the design and verification of a custom controller for analog components. The controller interfaces with SPI, Ethernet, and AXI to drive internal components and transmit data.

Responsibilities:
  • Develop UVM/Python tests for driving VIPs and stimulus drivers.
  • Create test components such as monitors, scoreboards, and Python models.
  • Manage coverage closure, GLS bring-up, and testing.
    • Experience:
    • 6+ years in verification methodologies using UVM and SystemVerilog.
    • Experience developing and maintaining verification testbenches, test cases, and environments.
    • Knowledge of all verification lifecycle aspects, including SDF and GLS simulations.
    • Required experience with Ethernet and SPI.
    • Over 5 years of UVM/SystemVerilog experience.
    • High proficiency in Python.
    • Experience with assertions and formal verification is a plus.
    • Preferred experience in Ethernet, SPI, AXI, JTAG, analog, and real number modeling.
    Skills:
    • UVM/SystemVerilog
    • Design Verification
    • Ethernet, SPI, AXI, JTAG
    • SDF and GLS simulations
    • Python
    Education:
    • Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field, or equivalent practical experience.
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