SerDes IC Packaging Technologist - Astera Labs : Job Details

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This range is provided by Astera Labs. Your actual pay will be based on your skills and experience — talk with your recruiter to learn more.

Base pay range

$215,000.00/yr - $240,000.00/yr

Additional compensation types

Annual Bonus and RSUs

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Senior Technical Recruiter @ Astera Labs | Licensed Talent Advisor

Job Description:

We are seeking an experienced and hands-on IC Packaging Technologist to lead and innovate in the development of high-performance, high-speed, and advanced IC package solutions. The ideal candidate will bring a proven track record of deep technical contributions in2.5D/3D integration, chiplet technology, fan-out wafer-level-packaging (e.g., FOWLP/FoCoS/Info), and heterogeneous integration. The successful candidate will lead strategic roadmap execution and scale innovative package solutions into production through close collaboration with OSATs, foundries and key suppliers

Basic Qualifications:

• M.S. or Ph.D. in Electrical Engineering, Materials Science, or related discipline.
• 10+ years of experience in IC packaging development and NPI for high-speed SerDes and high-performance SoCs, ASICs, or memory products
• Deep hands-on expertise with FCBGA, fcCSP, co-packaged optics (CPO), and 2.5D/3D integration technologies such as CoWoS, RDL and silicon interposers, and chiplet-based architectures (e.g., BoW, UCIe); along with experience in fan-out wafer-level packaging (FOWLP/WLFO).
• Strong understanding of packaging material selection, substrate stack-up, bump/RDL design, and DFM for advanced nodes
• Entrepreneurial, open-minded behavior and hands-on work ethic with the ability to prioritize a dynamic list of tasks.

Required Experience:

• Led multiple end-to-end advanced packaging NPI programs, from concept definition, pathfinding, design, supplier engagement, process development, and successful transition to HVM.
• Experience in high-speed SerDes IC package development, including interfaces such as PCI Express (PCIe) Gen4/Gen5/Gen6, CXL (Compute Express Link), and other multi-gigabit transceiver protocols, as well as devices such as retimers, switches, and PHYs operating at data rates up to 224G/448G PAM4.
• Experience defining RDL and bump architectures to enable die-to-die chiplet integration using interconnect standards such as BoW (Bunch of Wires) and UCIe (Universal Chiplet Interconnect Express).
• Demonstrated ability to lead collaboration with foundries (e.g., TSMC), OSATs, and substrate suppliers for collaborative package technology development.
• Deep understanding of mechanical (e.g., warpage, CTE mismatch), thermal (e.g., heat dissipation, TIM), and electrical (e.g., parasitics, signal integrity) design trade-offs in advanced package development, with a proven ability to deliver robust and manufacturable packaging solutions.
• Deep understanding of the technology landscape, cost drivers, and market trends influencing IC packaging innovation.
• Demonstrated ability to operate cross-functionally across design, product/test engineering, operations, reliability, marketing, and customer-facing teams.

Preferred Experience:

• SI/PI knowledge is a plus: SI/PI concepts, S-parameter extraction, and PDN optimization using HFSS, SIwave, or Ansys Designer
• Knowledge of EDA design tools is a plus: Cadence Allegro/APD, Altium,etc.

Seniority level

• Seniority levelMid-Senior level

Employment type

• Employment typeFull-time

Job function

• Job functionDesign
• IndustriesSemiconductor Manufacturing and Computer Hardware Manufacturing

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Medical insurance

Vision insurance

401(k)

Child care support

Paid maternity leave

Paid paternity leave

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