Principal FPGA Design Engineer - Cadence : Job Details

Cadence is a pivotal leader in electronic design, building on more than 30 years of computational software expertise. The company applies its Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence serves customers across consumer, hyperscale computing, 5G, automotive, aerospace, industrial and health markets.

$131,600.00/yr - $244,400.00/yr

• Protium is a leading product in FPGA Emulation/Prototyping domain. Design, verification, timing closure and hardware validation of the FPGA IPs.
• Develop FPGA IPs for the Protium platform, including design, verification, integration, timing closure, documentation and releasing the IPs to end users.
• Work on FPGA IP design, verification/simulation, timing closure and validation of IP on hardware.
• Enhance current IPs and develop new IPs.
• Debug and fix internal regression failures for FPGA IPs.
• Documentation of IPs.

• Master degree in Electrical Engineering with 5+ years of experience
• Experience with FPGA design and verification using Verilog
• Experience with high-end Xilinx (AMD) FPGAs including using Vivado for simulation, place and route
• Experience debugging FPGAs in the lab using Vivado hardware manager, debugging with firmware/software
• Experience using Linux servers, script development using Shell/Perl/TCL
• Experience using Cadence Simulators Incisive or Xcelium
• Detailed knowledge of industry standard interfaces such as PCI Express, DRAM/DDR4, SRAM, I2C, JTAG, AXI

• Seniority level: Mid-Senior level
• Employment type: Full-time
• Job function: Engineering and Information Technology
• Industries: Software Development

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