Job Location : all cities,NJ, USA
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Airspan Networks is a global provider of innovative 4G and 5G network solutions, enabling efficient and cost-effective connectivity for operators, enterprises, and industrial applications. We are looking for a motivated Junior UVM SystemVerilog Verification Engineer to join our dynamic team and contribute to the validation and testing of our cutting-edge communication technologies.
Job Description
As a Junior UVM SystemVerilog Verification Engineer, you will be responsible for assisting in the development and execution of test plans using Universal Verification Methodology (UVM) to validate the functionality, performance, and reliability of Airspan's FPGA designs. You will work closely with senior engineers to gain hands-on experience in digital design verification.
Key Responsibilities:
Qualifications & Experience:
Preferred Skills:
Why Join Us?
At Airspan, you'll work in an environment that values flexibility and innovation. Whether you're an experienced professional or looking to grow your career, you'll be joining a team that prioritizes collaboration and creativity. Be part of a company with a global reach, a strong track record, and an exciting vision for the future of wireless connectivity.
Apply today and help us drive the future of telecommunications!
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