GPU Formal Verification Engineer - Consol Partners : Job Details

6+ Month W2 Contract

Location: On-site in Austin, TX, or San Jose, CA 5 days a week.

Interviews: 1-2 Interviews

Start date: ASAP

Skills:

• Good understanding of CPU and/or GPU design architecture
• Strong experience or exposure to System Verilog (SV) and System Verilog Assertion (SVA) coding skills is required
• Experience in developing formal verification setups is a must
• Experience in developing constrained random testbenches is preferred
• Experience with formal verification tools such as VC Formal, Jasper Gold, or Questa Formal
• Experience working in a Linux environment

Job Description:

GPU designs provide a wealth of technical challenges in memory hierarchy, parallel processing units, and complex mathematical units.

This is a challenging and rewarding position where you will learn cutting-edge design and verification techniques from an exceptionally talented team, and where your contributions will make a visible impact to the end product.

You will be responsible for developing formal constraints, checks, and cover properties to new and existing design blocks towards verifying sequential equivalence for clock gating logic & so, verifying design features using assertions and verifying datapath equivalence of C and RTL models.

You will diagnose formal failures and work closely with RTL designers to update formal setup or RTL code.

• Develop formal verification setup using System Verilog modules and Assertions
• Run formal verification checks, analyze the results, and debug any issues.
• Develop and enhance constraints, checks, and cover points to achieve verification quality.
• Verify GPU design blocks using formal verification approaches like sequential equivalence checking, property-based feature verification and datapath verification using C models.
• Hands-on experience in developing formal based datapath verification setups using RTL & C Models
• Hands-on experience in developing formal property-based feature verification setups
• In-depth expertise on proof depth and convergence analysis for formal setups
• Root cause formal failures to identify design or test setup issues.
• Analyze and deploy formal convergence techniques like abstraction, blackboxing and design reductions.
• Work closely with cross-functional teams, including design, architecture, and software teams, to ensure that verification efforts are aligned with project goals and requirements.
• Participate in the development and improvement of verification methodologies, tools, and flows to increase efficiency and effectiveness of verification efforts.
• Adhere to project execution and planning approaches using Confluence, JIRA and relevant techniques.
• Create and maintain documentation for formal verification test plans, convergence reports, complexity analysis reports and results.
• Responsible in driving formal verification tasks & report to project verification leads as required

Requirements Qualifications

• BSEE, Computer Engineering, or Computer Science bachelor's degree and a minimum of 3+ years of experience o Masters or Ph.D. degree preferred
• Excellent communication skills and be able to work with cross-functional teams to execute verification plan