FPGA Designer with Security Clearance - L3Harris Technologies : Job Details

Job Title: Sr ASIC/FPGA VHDL Design Engineer Job Code: 24260 Job Location: Camden, NJ-relocation available for those that qulify Schedule: 9/80 Regular with every other Friday off Job Description: Reporting to the Manager, Engineering (ASIC/FPGA), the Senior Member of Engineering Staff (SMES) will be part of the key design team, responsible for the delivery of FPGAs for defense applications. S/he will architect, implement FPGA design, with hands on design/debug with primarily Ethernet, I2C, SPI, AXI protocols. L3Harris has state-of-the-art EDA flows/methodologies including Mentor EDA: Simulator Questa Prime, Verification IP (QVIPs), UVM framework, Clock Domain Crossing (CDC), Reset Domain Crossing (RDC), Questa Lint, Synopsys (DC/Primetime/Synplify), Xilinx/Intel/Microchip EDA (Vivado/Libero/Quartus). We are a learning organization and have the capability to target all FPGA vendors and have ASIC front end capability, with mature design processes. This is a high impact role in the organization to ensure robust quality and delivery of communication products for National Security. Essential Functions: Derive FPGA design specifications from system requirementsDevelop detailed FPGA architecture for implementationImplement design in RTL (VHDL) and perform module level simulationsPerform Synthesis, Place and Route (PAR) and Static Timing Analysis (STA)Perform RTL quality using: Lint, Reset Domain Crossing (RDC), Clock Domain Crossing (CDC) , Static Formal EDAGenerate verification test plans and perform End to End SimulationsSupport Board, FPGA bring upValidate design through HW/SW integration test with test equipmentSupport product collateral for NSA certification Qualifications: Bachelor of Science (BS) -Four year degree or Masters (MS) or PhD from an accredited course of study in engineering, engineering technology (chemistry, physics, mathematics, data science, or Electrical/Electronics/Computer Engineering/Computer Science)3-5+ years' experience designing FPGA products with VHDLExperience with Xilinx FPGAs and VivadoExperience with Revision control systemExperience with Earned Value Management (EVM)Good written, verbal, and presentation skillsActive DoD Security Clearance Preferred Additional Skills: Experience with mapping algorithms to architectureExperience in C++ (OOP)Experience with any of protocols : Ethernet, TCP/IP, PCIe, NVMe, USBExperience with Xilinx SoC design with SDKs and PetaLinux OSExperience with High-Level Synthesis (HLS) with Vivado HLX or Mentor Catapult