Skills and Responsibilities:
ASIC/IP RTL to Emulation platforms (Preferred: Zebu, Palladium)Build model from released RTLGenerate target platform loadable image(s), test and release the image to Firmware and DV teams.Run sanity tests for qualifying release of the image(s)Release the model to various teams including Functional Validation team, Firmware, DVAssist debug of failures providing instrumented model (Waveform Dumps, in circuit debug) and interfacing with stakeholders.Coordinate with Tools team to validate tool and Model releaseFPGA and Emulator flows and methodologiesExperience with Daughtercards, Speedbridges, Virtual PrototypingHardware emulators, such as Zebu is a must have, Palladium is appreciatedEmulation methodologies, including in-circuit emulation, hybrid systems, or simulation accelerationStrong knowledge of Complete Design Cycle to understand the Different IP designs to integrate In the buildSimulation acceleration knowledge (DPI and Transactors)In depth understanding of RTL and SynthesisLogic simulation: VCS/NCSIMProgramming/scripting skills (C, C++, Python)Experience with CPU integration is a big plus, especially ARM/RISC-V CPUKnowledge of CoreSight/UltraSoC debug infrastructure integration is a plusKnowledge of OS kernel and experience in driver developmentExperience with FPGA and/or Emulation platformsExperience with lab system debug with logic analyzers, scopes, meters etc.Additional Skills:
PROTOTYPESELF MOTIVATEDSTRUCTURED SOFTWAREPROTOTYPINGPYTHONSCRIPTINGSOCTCLUSBALGORITHMARCHITECTUREDEBUGFIELD PROGRAMMABLE GATE ARRAYFIRMWARELOGIC ANALYZERSPCI EXPRESSPERFORMANCE MODELINGAdditional Job Details: 1 - Concept Prototyping (P3 - Advanced) | 2 - Firmware Engineering (P3 - Advanced)
Primary Skill: Python
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